`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:29:31 04/20/2011 
// Design Name: 
// Module Name:    Mux_4to1_16bits 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Mux_4to1_16bits(a, b, c, d, sel, out);
    input [15:0] a;
    input [15:0] b;
    input [15:0] c;
    input [15:0] d;
    input [1:0] sel;
    output [15:0] out;
    
	 reg [15:0] out;

	always @ (*)
	begin
		case (sel)
			2'b00: out <= a;
			2'b01: out <= b;
			2'b10: out <= c;
			default: out <= d;
		endcase
	end

endmodule
